1. Field of the Invention
The present invention pertains to the field of electronic design automation (EDA). More particularly, this invention relates to the art of optimizing differential pairs.
2. Background
Advances in technology have lead to increasingly complex circuits. At the board level, circuits are routinely composed of dozens of complex very large scale integration (VLSI) components. Hundreds, or even thousands, of conductive traces may be routed in one or more layers of a printed circuit board (PCB) to selectively connect the components. At the chip level, integrated circuit design is moving toward even more complex circuits, wherein an entire system can often be routed on a single chip. At both levels, every trace must meet a number of constraints, such as signal integrity and minimum and maximum signal delays. It would be incredibly time consuming, if not physically impossible, for a person to manually route all of the physical traces, and verify all of the signal constraints, in today""s complex electronic designs.
Even as complexity increases, however, market pressures require shorter design cycles. The pace of competition will not allow a designer to spend countless hours routing a design on a chip or PCB manually. As a result, designers are always looking for ways to streamline the design process.
One simplification involves designing at a higher level of abstraction. In other words, a designer can provide a description of a circuit design, such as a xe2x80x9cnetlist,xe2x80x9d to an electronic design automation (EDA) system. A netlist generally specifies all of the component connections in a circuit design. A netlist may also include physical dimensions of components in the design, the dimensions of the PCB or chip to which the components are coupled, pin locations for the components and PCB or chip, the location of components on the PCB or chip, as well as certain employment rules such as timing constraints and minimum spacing requirements.
From a netlist, an EDA system can attempt to route all of the traces automatically. Depending on the complexity of the design, and the employment rules, an EDA system may or may not be able to route all of the traces. If the EDA system cannot make all of the necessary connections, or the timing constraints cannot be met, a designer will normally have to make adjustments to the design and run it through the EDA system again. Many iterations may be necessary to produce a functional circuit layout. Each iteration consumes valuable computer time and adds cost to the design.
Therefore, EDA systems need to be improved. In particular, a need exists for an improved method and apparatus to optimize differential pairs based on timing constraints.
A method to optimize differential pairs, based on timing constraints, includes recognizing that two separate traces form a differential pair, and combining sections of the differential pair into one or more trunks. Then, a propagation delay is determined over the differential pair. The determined propagation delay is compared to a timing constraint for the differential pair. If the timing constraint is not met, a length of one or more of the trunks is adjusted and the propagation delay is redetermined and compared to the timing constraint. If the timing constraint is still not met, the process is repeated until the timing constraint is met or until the timing constraint cannot be met. If the timing constraint is eventually met, the one or more trunks are used to produce an adjusted differential pair.